LandOffer
Semiconductor Device Modeling Engineer
Job details
- Pay
- $173,660 – $330,340 a year
- Work mode
- On-site
- Employment
- Full-time
- Level
- Mid level
- Experience
- 3+ years
- Education
- Master's degree
- Posted
- Oct 30, 2026
- Last confirmed open
- Oct 31, 2026
What you'll need to apply
Fields this application requires
Company-specific questions
- 1) * As of today's date, are you 18 years of age or older?
- 2) * Are you a current or former employee of Ernst & Young?
- 3) * Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 4) * To the best of your knowledge and belief, are you aware of a contract or agreement with your current employer (or other company), such as a non-competition, non-disclosure, or non-solicitation agreement, that impact or interfere with your ability to work for the Company or communicate with former colleagues about working at the Company
- 5) * Do you own, control, or have an economic interest in any intellectual property rights (patents, trademarks, or copyrights)?
- 6) * If hired, do you intend to (select all that apply):
- 7) * Are you a current employee of the US Department of Defense (DOD) or were you an employee of the US Department of Defense (DOD) on or after January 28, 2008?
- 8) * Are you a current Federal, State or Local Government employee; including military (other than the DOD) or have you at any time in the past 5 years been an employee of one of these entities?
- 11) * Do you now, or in the future, require Intel to sponsor you for a visa to work in the United States? NOTE: Individuals with work authorization issued pursuant to their student visa ( e.g., F-1, J-1, M-1 ) or currently on work visas specific to their current employer ( e.g., H-1B, O-1, TN, H-1B1, E-3 ), should answer “Yes” because Intel must file a visa petition on your behalf now or in the future. Intel immigration sponsorship refers to Intel filing employment-based visa and permanent resident applications on behalf of the employee in order for the individual to have the legal right to work in the U.S. Individuals with work authorization not dependent on Intel sponsorship should respond “No”, e.g., Family based immigration, DACA, TPS, PIP, & Asylum Applicant.
About this role
Job Details
Job Description:
About the team and organization
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies.
As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.
Qualifications
- Minimum qualifications are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Master's degree in Electrical Engineering or a related discipline and at least 5+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field.
- 3+ years of hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
- Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
- Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling.
- Experience developing LLE models for FinFET or GAAFET technologies.
- Skilled in Python scripting for automation and documentation.
Preferred Qualifications
- Ph.D. in Electrical Engineering or a related discipline with 8+ years of industry experience in the semiconductor field.
- Deep expertise in compact modeling, including one or more of the following areas:
- Layout-dependent effects (LDE) and their impact on circuit performance.
- Modeling using Open Model Interface (OMI)
- Strong understanding of process flow, layout, and basic circuit design/simulation.
- Modeling self-heating effects and their influence on device and circuit performance.
- Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
- o Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
- Experience with machine learning algorithms and their application is data analysis and compact model development.
Job Type
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .
Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.