SoC Physical Design Engineer

Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities.

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Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors.

Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

As a Physical Design Engineer, you will collaborate closely with System-on-Chip (SoC) architects, front-end and back-end hardware designers, and power/performance teams to drive the physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes.

You will be responsible for developing custom methodologies across the physical design cycle – including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis – to optimize the power, performance, and area of the design while ensuring overall convergence. You will have the opportunity to bring cutting-edge technologies into a high-volume consumer product.

Responsibilities

• Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy
• Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency
• Identify and resolve physical implementation bottlenecks related to congestion, timing, and power; then develop automation and AI-assisted flows to improve throughput and QoR
• Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure
• Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements
• Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements
• Drive EDA vendor engagement, tool evaluations, and flow improvements

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in SoC or ASIC physical design
• Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff
• Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS
• Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects
• Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent
• Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL
• Experience collaborating across RTL, DV, DFx, package, and vendor teams Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure
• Track record of defining signoff criteria and leading tapeout execution
• Tapeout experience at 3nm or below
• Experience adhering to and implementing responsible, ethical AI practices (e.g. risk assessment, bias mitigation, quality and accuracy reviews)
• Experience applying ML-driven implementation (e.g. DSO.ai/Cerebrus) or LLM agents to flow debugging/QoR with measurable impact
• Demonstrated ongoing AI skill development (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
• Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring
• Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion
• Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques
• Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs
• Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies
• Master’s or PhD degree in Electrical Engineering, Computer Engineering, or equivalent area