Yield Development Engineer
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Fields this application requires
Company-specific questions
- 1. Are you a current or former employee of Ernst & Young?
- 2. Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 3. Did you sign any non-competition or non-solicitation agreement with your current employer (or other company) that might impact or prevent you to work in any way for Intel?
- 4. Do you own, control or have an economic interest in any intellectual property right (patents, trademarks, or copyrights)?
- 5. If hired, do you intend to maintain any secondary non-Intel employment or engage in a non-Intel business activity? If yes, please note that such employment or activity may be subject to review and approval.
- 6. I understand and agree that any false information, misrepresentation, or omission of facts in this document or in any document I have completed or supplied regarding my application for employment will be considered as dishonest and deception, as such, justification for refusal to hire, or immediate termination of employment without recourse.
- 7. Are you legally entitled to work in the country/countries for which you are applying and can provide evidence?
- 8. Are you a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? Do you have any close relationship (such as a family member) with a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? If you answer Yes to one of the questions or both questions, respond Yes.
About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
The Role and Impact
As a Yield Development Engineer, you will play a critical role in advancing Intel's manufacturing capabilities by driving technology yield improvements. You will work hands-on to identify yield limiters, conduct statistical analyses, and collaborate on process changes to optimize manufacturability.
Your contributions will directly impact product quality, factory efficiency, and Intel's ability to deliver cutting-edge technologies to market.
Business group
The Intel Foundry team focuses on delivering high-performance solutions that empower customers across the globe. As part of this team, you will contribute to innovative process development and yield optimization efforts, supporting Intel's mission to lead in advanced semiconductor manufacturing. The group emphasizes collaboration and technical excellence to enable breakthrough innovations and industry-leading outcomes.
Key Responsibilities
- Identify and analyze yield limiters using statistical techniques and big data methodologies.
- Develop and implement process development roadmaps to support technology yield milestones.
- Consolidate, interpret, and visualize diverse data sources to extract actionable insights for yield enhancement.
- Perform fault isolation and failure analysis to identify root causes of failures.
- Collaborate across design, test, and process teams to debug yield limiters and ensure manufacturability.
- Develop measurement recipes and harden equipment capabilities for advanced logic nodes.
- Execute new product introductions, design-technology co-optimization, and factory experiments to drive yield improvements.
- Create tools, algorithms, and systems to perform high-volume data analysis and advance yield modeling.
- Drive cross-functional collaborations to resolve issues in yield, product design, and manufacturing processes.
Qualifications
Bachelor's degree in electronic engineering, Computer Engineering or in a related field
Technical Skills
- 3+ years of experience in semiconductor failure analysis or test engineering
- Strong understanding of Array architecture and failure mechanisms or hands-on experience with SCAN ATPG methodology, including Scan chain diagnosis, ATPG pattern generation and debug, Fault models (stuck-at, transition, path delay, bridging)
- Proficiency in fault isolation techniques, including Electrical fault isolation (EFI), circuit, and layout analysis
- Familiarity with failure signature analysis and yield learning
Debug and Analysis
- Experience debugging logic and memory/array failures from silicon bring-up through production
- Ability to correlate ATE test results with design and process data
- Experience with tester platforms (e.g., Advantest, Teradyne)
- Understanding of DFT (Design for Testability) concepts and implementation
Preferred Qualifications
- Experience with embedded memory compilers and array redundancy analysis
- Familiarity with statistical data analysis tools (JMP, Python, R)
- Experience with nanometer process nodes (7nm, 5nm, 3nm, or below)
- Background in BIST (Built-In Self-Test) for memory and logic
- Exposure to machine learning-based fault classification or yield analysis
- Experience collaborating with design, process, and layout teams for root cause analysis
Soft Skills and Work Style
- Strong analytical and problem-solving skills
- Ability to work in a fast-paced, cross-functional environment
- Excellent communication skills to present findings to engineering and management teams
- Self-motivated with ability to manage multiple debug cases simultaneously
- Team player with experience working across design, process, and manufacturing organizations
Job Type:
Experienced Hire
Shift:
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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