Staff SOC DFT Engineer
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Company-specific questions
- 1. Are you a current or former employee of Ernst & Young?
- 2. Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 3. Did you sign any non-competition or non-solicitation agreement with your current employer (or other company) that might impact or prevent you to work in any way for Intel?
- 4. Do you own, control or have an economic interest in any intellectual property right (patents, trademarks, or copyrights)?
- 5. If hired, do you intend to maintain any secondary non-Intel employment or engage in a non-Intel business activity? If yes, please note that such employment or activity may be subject to review and approval.
- 6. I understand and agree that any false information, misrepresentation, or omission of facts in this document or in any document I have completed or supplied regarding my application for employment will be considered as dishonest and deception, as such, justification for refusal to hire, or immediate termination of employment without recourse.
- 7. Are you legally entitled to work in the country/countries for which you are applying and can provide evidence?
- 8. Are you a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? Do you have any close relationship (such as a family member) with a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? If you answer Yes to one of the questions or both questions, respond Yes.
About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
The Role and Impact
Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of complex SoC (System-on-Chip) designs. You will work closely with cross-functional teams, influencing designs from concept to production, and ensuring our products meet the highest quality standards.
In this role, you will develop innovative DFT/DFD methodologies, optimize workflow with AI, and enhance post silicon efficiency. Your work will directly impact Intel's ability to deliver world-class semiconductor solutions that advance technology across industries.
Key Responsibilities :
- Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
- Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements.
- Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements.
- Collaborate with post-silicon teams to debug and validate DFT features.
- Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows.
Qualifications
Minimum Qualifications :
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
- Expertise in RTL design using hardware description languages like Verilog, VHDL, or SystemVerilog.
Preferred Qualifications :
- Familiar with AI application.
- Familiarity with advanced DFT methods for low-power or high-performance SoC designs.
- Understanding of industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), or IEEE 1500 (Core Test).
- Advanced knowledge of industry-standard DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus.
- Knowledge of Python or other scripting languages for design automation.
- Hands-on experience with managing multi-functional teams or complex SoC projects.
We are looking for a visionary DFT engineer who thrives in a collaborative and innovative environment, and who is excited by the opportunity to contribute to groundbreaking technology. Join us to shape the future of computing and leave your mark on the world.
Job Type
Experienced Hire
Shift:
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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