Senior Physical Design Engineer
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Company-specific questions
- 1) * As of today's date, are you 18 years of age or older?
- 2) * Are you a current or former employee of Ernst & Young?
- 3) * Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 4) * To the best of your knowledge and belief, are you aware of a contract or agreement with your current employer (or other company), such as a non-competition, non-disclosure, or non-solicitation agreement, that impact or interfere with your ability to work for the Company or communicate with former colleagues about working at the Company
- 5) * Do you own, control, or have an economic interest in any intellectual property rights (patents, trademarks, or copyrights)?
- 6) * If hired, do you intend to (select all that apply):
- 7) * Are you a current employee of the US Department of Defense (DOD) or were you an employee of the US Department of Defense (DOD) on or after January 28, 2008?
- 8) * Are you a current Federal, State or Local Government employee; including military (other than the DOD) or have you at any time in the past 5 years been an employee of one of these entities?
- 11) * Do you now, or in the future, require Intel to sponsor you for a visa to work in the United States? NOTE: Individuals with work authorization issued pursuant to their student visa ( e.g., F-1, J-1, M-1 ) or currently on work visas specific to their current employer ( e.g., H-1B, O-1, TN, H-1B1, E-3 ), should answer “Yes” because Intel must file a visa petition on your behalf now or in the future. Intel immigration sponsorship refers to Intel filing employment-based visa and permanent resident applications on behalf of the employee in order for the individual to have the legal right to work in the U.S. Individuals with work authorization not dependent on Intel sponsorship should respond “No”, e.g., Family based immigration, DACA, TPS, PIP, & Asylum Applicant.
About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
About the Role
Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies.
What You’ll Do
Key responsibilities will include but not limited to:
- Own physical design and implementation of CPU core blocks or subsystems
- Execute synthesis, floorplanning, place and route, and design closure
- Perform static timing analysis (STA), power analysis, and physical verification
- Drive convergence of timing, power, and area (PPA) metrics
- Debug and resolve complex design issues across multiple design stages
- Develop and optimize design flows and automation scripts
- Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams
- Contribute to improving design methodologies and best practices
- Provide guidance to junior engineers where applicable
Behavioral traits that we are looking for:
- Strong problem-solving and analytical thinking
- Takes ownership and accountability for deliverables
- Collaborates effectively across multidisciplinary teams
- Communicates technical concepts clearly and concisely
- Prioritizes work effectively in a fast-paced environment
- Continuously learns and applies new tools and methodologies
Why Join Us
- Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
- Be part of a team driving innovation at advanced semiconductor process nodes
- Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design
- Collaborate with experienced engineers across architecture, design, and full-chip integration
- Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities
- Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
- See Intel Benefits for more details.
Qualifications
- You must possess the below minimum qualifications to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note
For information on Intel’s immigration sponsorship guidelines, please see
Intel U. S. Immigration Sponsorship Information
Minimum Qualifications and Experience :
Bachelors in Computer / Electrical Engineering or related field with 7+ years of relevant work experience. Or a Masters in the same field with 4+ years of relevant work experience.
Your experience described above must be in the following:
- Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
- PV convergence (including static timing and power analysis)
- Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
- Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
- Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
Preferred Qualifications and Experience :
- Industry experience/exposure with CPU Micro-Architecture
- Physical design best known practices concerning floor-planning, routing techniques, clock distribution
- Static Timing Analysis, Noise analysis, and reliability verification techniques
- RTL to GDS methodologies and formal equivalence
- Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .
Annual Salary Range for jobs which could be performed in the US: $141,910. 00-269,100. 00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.