LandOfferMemory Electrical Validation Engineer
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Company-specific questions
- 1. Are you a current or former employee of Ernst & Young?
- 2. Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 3. Did you sign any non-competition or non-solicitation agreement with your current employer (or other company) that might impact or prevent you to work in any way for Intel?
- 4. Do you own, control or have an economic interest in any intellectual property right (patents, trademarks, or copyrights)?
- 5. If hired, do you intend to maintain any secondary non-Intel employment or engage in a non-Intel business activity? If yes, please note that such employment or activity may be subject to review and approval.
- 6. I understand and agree that any false information, misrepresentation, or omission of facts in this document or in any document I have completed or supplied regarding my application for employment will be considered as dishonest and deception, as such, justification for refusal to hire, or immediate termination of employment without recourse.
- 7. Are you legally entitled to work in India for which you are applying and can provide evidence?
- 8. Are you a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? Do you have any close relationship (such as a family member) with a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? If you answer Yes to one of the questions or both questions, respond Yes.
About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
The Role and Impact:
As a Memory Electrical Validation Engineer, you will play a pivotal role in optimizing and validating electrical performance for memory IO interfaces. You'll focus on ensuring compliance with industry standards, analyzing margins for stable operation, debugging electrical issues, and driving system-level improvements.
Your expertise will directly contribute to delivering high-quality, reliable products that meet production goals while advancing Intel's innovative memory solutions.
Business group
The Silicon and Platform Engineering (SPE) Group leads Intel's efforts in designing, developing, and validating advanced silicon and platform technologies. This team is committed to delivering cutting-edge solutions that drive Intel's leadership in the semiconductor industry.
By joining SPE, you'll be part of a collaborative environment that tackles challenging problems and powers Intel's success in creating transformative technologies for the future.
Key Responsibilities
- Define electrical validation strategies for memory IO interfaces to ensure optimized electrical performance and alignment with production goals.
- Validate circuit analog performance, signal integrity compliance, and system-level margins against industry standards.
- Analyze, debug, and optimize Memory Reference Code (MRC) requirements to improve margins and overall product quality.
- Collaborate on multidisciplinary research for testing, validation, and optimization of memory IO and mixed-signal architectures.
- Develop procedures and designs for validation processes, systems margin evaluation, and test infrastructure.
- Debug functional and triage failures to identify root causes and resolve electrical issues.
- Test electrical interactions between design features using advanced validation infrastructure.
- Prepare validation specifications, evaluate intellectual property (IP), and generate detailed test reports.
- Partner with architecture, design, and presilicon verification teams to ensure effective Design for Testability (DFT) and Design for Manufacturability (DFM) capabilities for IO architectures.
Qualifications
Minimum Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of hands-on industry experience in electrical validation or debugging
- Proficiency in validating signal integrity and electrical performance of memory IO interfaces.
- Experience with debugging electrical and system-level issues.
- Demonstrated ability to analyze, design, and optimize validation procedures and test infrastructure.
- Familiarity with compliance testing against industry-standard specifications.
Preferred Qualifications:
- Familiarity with memory validation tools, techniques, and methodologies.
- Strong collaborative skills, particularly in multidisciplinary research and cross-functional teamwork.
- Proven ability to develop and refine validation strategies for complex architectures.
- Passion for delivering innovative solutions and driving continuous improvement.
We're looking for someone eager to make a meaningful impact while solving complex challenges in memory validation. If you're ready to join a team that values collaboration, innovation, and excellence, we encourage you to apply today.
Job Type
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.