Formal Verification Engineer
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Company-specific questions
- 1. Are you a current or former employee of Ernst & Young?
- 2. Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
- 3. Did you sign any non-competition or non-solicitation agreement with your current employer (or other company) that might impact or prevent you to work in any way for Intel?
- 4. Do you own, control or have an economic interest in any intellectual property right (patents, trademarks, or copyrights)?
- 5. If hired, do you intend to maintain any secondary non-Intel employment or engage in a non-Intel business activity? If yes, please note that such employment or activity may be subject to review and approval.
- 6. I understand and agree that any false information, misrepresentation, or omission of facts in this document or in any document I have completed or supplied regarding my application for employment will be considered as dishonest and deception, as such, justification for refusal to hire, or immediate termination of employment without recourse.
- 7. Are you legally entitled to work in India for which you are applying and can provide evidence?
- 8. Are you a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? Do you have any close relationship (such as a family member) with a government official who has worked or is working with Intel on government related business in the last twelve months or is reasonably likely to work with Intel in the next six months? If you answer Yes to one of the questions or both questions, respond Yes.
About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
The Role and Impact
Intel is seeking a Formal Verification Engineer for the Silicon Chassis team. In this role, you will apply advanced formal methods to rigorously verify interconnect fabrics, protocol bridges, and link-layer logic. You will drive end-to-end formal verification processes, including property specification and proof convergence across multiple protocol domains.
Through close collaboration with architecture, design, and software teams, your work will ensure the delivery of high-quality, cutting-edge solutions.
Business Group
The Central Engineering Group (CEG) focuses on enabling technology innovation across Intel by delivering robust engineering solutions and methodologies. As part of this group, the UIC Validation Transport team plays a critical role in supporting Intel's broader goals of advancing silicon development.
By leveraging formal verification techniques, this team ensures the reliability and performance of foundational technologies used in Intel's products worldwide.
Key Responsibilities
- Develop and execute formal verification test plans, including defining scope, strategies, and methodologies.
- Create abstraction models to facilitate convergence on complex designs and apply abstraction techniques for formal analysis.
- Generate and validate proofs to verify designs, troubleshoot failing tests, and implement corrective measures.
- Collaborate across architecture, RTL design, and physical implementation teams to improve verification accuracy for advanced features.
- Maintain and enhance formal verification tools, methodologies, and infrastructure for optimized workflows.
- Simplify and model design verification challenges using architecture-level modeling techniques.
- Utilize formal verification tools to resolve Binary Decision Diagrams (BDD) complexities and optimize data paths.
- Document verification plans, track progress, and lead technical reviews with cross-functional teams.
Qualifications
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 4+ years of professional experience in formal verification OR Master's degree in a relevant field, with 3+ years of experience OR PhD with no prior professional experience.
- Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.
- Strong knowledge of System Verilog, Verilog, and fundamentals of logic/microarchitecture.
- Experience with abstraction modeling, simulation techniques, and convergence strategies.
- Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).
Preferred Qualifications
- Proven ability to resolve complex architectural and formal verification challenges.
- Strong collaboration and teamwork skills, with experience in cross-functional environments.
- Exceptional technical documentation and communication abilities.
- Enthusiasm for driving innovation and improving verification tools and methodologies.
Join us in shaping the future of computing technology with Intel by contributing to groundbreaking advancements in the field of formal verification.
Job Type
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.