CPU Front-end Design Manager
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- 1. Are you a current or former employee of Ernst & Young?
- 2. Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
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About this role
Employer-provided description, formatted for easier reading.
Job Details
Job Description:
Intel's P-Core organization is seeking a highly experienced engineering manager to lead the Memory Execution Unit (MEU) Front-End development team responsible for delivering world-class CPU microarchitecture solutions for next-generation Server and Client products.
The manager will own end-to-end execution of the MEU cluster across RTL Design, Design Verification, and Formal Verification, driving feature development from architecture definition through RTL implementation, pre-silicon validation, quality signoff, and silicon readiness.
This role requires a strong technical leader who can build and grow a high-performing organization, drive execution excellence, influence cross-functional stakeholders, and deliver predictable first time-right silicon.
Key Responsibilities
Technical Leadership
- Own end-to-end delivery of the MEU cluster across RTL, DV, and Formal Verification functions.
- Drive microarchitecture reviews, implementation strategy, verification closure, and quality signoff.
- Ensure delivery of features meeting Power, Performance, Area (PPA), Quality, Reliability, and Security objectives.
- Define execution strategy, milestones, risk mitigation plans, and resource allocation.
- Drive adoption of advanced methodologies, automation, AI-assisted debug, formal technologies, and verification innovations.
People Leadership
- Lead and grow an experienced team of RTL, DV, and Formal Verification engineers and technical leads.
- Build leadership bench strength and succession plans.
- Drive talent development, mentoring, career growth, retention, and organization health.
- Foster a culture of innovation, collaboration, accountability, and continuous improvement.
Cross-Functional Collaboration - Partner with Architecture, Design, Validation, Physical Design, DFT, Power, Security, and Product Engineering teams. Influence technical decisions across multiple organizations and geographies. Drive effective stakeholder management and executive communication.
Quality and Execution Excellence - Deliver predictable execution against major CPU program milestones, bug prevention, early bug interception, coverage closure, and validation quality improvements. Ensure robust pre-silicon quality metrics and risk-based signoff methodology. Establish best practices for RTL, DV, and Formal Verification across the organization.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of industry experience, or Master's degree with 12+ years of experience.
- 5+ years of engineering management experience leading senior technical teams.
- Strong expertise in CPU microarchitecture, RTL design, verification methodologies, and formal verification.
- Proven experience delivering complex SoC/CPU products from definition through silicon.
- Deep understanding of SystemVerilog, verification methodologies, assertions, coverage-driven verification, and formal tools.
- Demonstrated success leading cross-functional programs and geographically distributed teams.
Preferred Qualifications
- Experience leading large Front-End CPU organizations spanning RTL, DV, and Formal Verification.
- Expertise in Out-of-Order CPUs, Memory Subsystems, Cache Coherency, or Execution Units.
- Strong understanding of performance, power, security, and quality tradeoffs.
- Experience driving AI/ML-based validation methodologies and automation initiatives.
- Proven track record of building high-performing organizations and developing future leaders.
- Strong executive communication and stakeholder management skills.
Job Type
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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