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ADCE Packaging Design Architect

Intel · US, Arizona, Phoenix · US, Oregon, Hillsboro · US, Washington, Multiple Cities · US, New Mexico, Albuquerque · US, Massachusetts, Beaver Brook · US, Colorado, Fort Collins · US, California, Santa Clara · US, California, Folsom · US, Texas, Austin

Spotted 48d agoFull-time

Job details

Work mode
On-site
Employment
Full-time
Level
Staff / principal
Experience
10+ years
Education
Master's degree
Posted
Sep 11, 2026
Last confirmed open
Oct 29, 2026

What you'll need to apply

Fields this application requires

NameEmailPhoneCountryResumeVisa sponsorship answerWork authorization answer

Company-specific questions

  • 1) * As of today's date, are you 18 years of age or older?
  • 2) * Are you a current or former employee of Ernst & Young?
  • 3) * Are you an immediate family member (parent, child, sibling, spouse/partner) of a partner at Ernst & Young who is based out of the San Jose, California office?
  • 4) * To the best of your knowledge and belief, are you aware of a contract or agreement with your current employer (or other company), such as a non-competition, non-disclosure, or non-solicitation agreement, that impact or interfere with your ability to work for the Company or communicate with former colleagues about working at the Company
  • 5) * Do you own, control, or have an economic interest in any intellectual property rights (patents, trademarks, or copyrights)?
  • 6) * If hired, do you intend to (select all that apply):
  • 7) * Are you a current employee of the US Department of Defense (DOD) or were you an employee of the US Department of Defense (DOD) on or after January 28, 2008?
  • 8) * Are you a current Federal, State or Local Government employee; including military (other than the DOD) or have you at any time in the past 5 years been an employee of one of these entities?
  • 11) * Do you now, or in the future, require Intel to sponsor you for a visa to work in the United States? NOTE: Individuals with work authorization issued pursuant to their student visa ( e.g., F-1, J-1, M-1 ) or currently on work visas specific to their current employer ( e.g., H-1B, O-1, TN, H-1B1, E-3 ), should answer “Yes” because Intel must file a visa petition on your behalf now or in the future. Intel immigration sponsorship refers to Intel filing employment-based visa and permanent resident applications on behalf of the employee in order for the individual to have the legal right to work in the U.S. Individuals with work authorization not dependent on Intel sponsorship should respond “No”, e.g., Family based immigration, DACA, TPS, PIP, & Asylum Applicant.
Job description

About this role

Job Details

Job Description:

Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout.

Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record.

Required Skills and Experience:

  • Self-motivated engineer who has strong technical background in design and electrical analysis.
  • Solid background in semiconductor fabrication and packaging
  • Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. - Ability to work independently and at various levels of abstraction
  • Strong organization, time management, and communication skills, self-motivated.
  • Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.
  • Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
  • Experience and knowledge with assembly process, test and characterization techniques preferred

Qualifications:

  • Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science.
  • 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.

Job Type

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Beaver Brook, US, New Mexico, Albuquerque, US, Oregon, Hillsboro, US, Texas, Austin, US, Washington, Multiple Cities

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position.

For additional questions, please contact your Recruiter.

Benefits

  • We offer a total compensation package that ranks among the best in the industry.
  • It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
  • Find out more about the benefits of working at Intel .
  • Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
  • Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
  • Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
  • Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 06/09/2026 * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
  • We do not charge any fees during our hiring process.
  • Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
  • If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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