ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

We are recruiting a ASIC Engineering Design Verification Leader to drive the design and verification of advanced optical transceivers and platforms for Cisco's data centre networking solutions. Lead verification documentation, develop testbench components, and collaborate with multidisciplinary teams. Ideal for experienced engineers with strong expertise in SystemVerilog, Python, C, and UVM.