Digital Design Manager

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.

Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www. asteralabs.

com .

Role Overview

This role will lead day-to-day DFT architecture and execution for Astera Labs' signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure. You will partner with design, verification, physical design, packaging, product engineering, and manufacturing teams to improve coverage, yield, diagnostics, and production readiness across advanced multi-die products.

As Astera Labs scales its purpose-built connectivity platform, you will help establish practical DFT methods for high-speed PCIe and Ethernet signal-conditioning products, with a strong focus on SerDes physical-layer performance, signal integrity, and production robustness.

The role offers hands-on technical ownership, opportunities to mentor engineers, and direct influence on products that keep next-generation AI systems connected, observable, and reliable.

Key Responsibilities

• DFT Architecture & Planning
• Define DFT plans for signal-conditioning products supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging configurations.
• Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.
• Partner with design and physical design teams to balance DFT area, timing, routing, and manufacturability.
• DFT Implementation & Silicon Readiness
• Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.
• Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.
• Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.
• Quality, Yield & Diagnostics
• Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.
• Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.
• Improve diagnostic capabilities for silicon, package, and system-level issues.
• Technical Leadership & Collaboration
• Mentor DFT engineers and coordinate execution across product development milestones.
• Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.
• Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10-15 years of experience in Digital Design engineering or related semiconductor design and test work.
• Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.
• Understanding of the ASIC design flow from RTL through GDS and DFT signoff.
• Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.
• Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.

Preferred Qualifications

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.
• Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.
• Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.
• Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.

Salary range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.