Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without.

It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Collaborating with the logic design team to understand partition architecture and proactively addressing physical design aspects early in the development cycle. Managing the complete netlist-to-GDSII implementation process for design partitions, ensuring that project schedules and design objectives are met.

Responsible for timing analysis, physical and electrical verification, and driving signoff closure for the partitions. Working closely with the architecture team to define, analyze, and document the micro-architecture specifications of various hardware design blocks.

Conducting feasibility analyses on proposed architectures and algorithms—evaluating aspects such as performance, area, timing, power consumption, complexity, and implementation effort. Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. Drive optimization of PnR partitions, to achieve best Power/Performance/Area.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role.

The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

Master’s Degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include

Using physical design concepts, construction and analysis flows and methodology to design SOC ASICs Utilizing Cadence/Synopsys EDA tools to perform Automatic Place and Route on partitions Optimizing logic placement and routing for best area, power, performance, including custom placement and routing using Cadence/Synopsys EDA tools Using floorplan, IO placement, and Macro placement to achieve high density layout design Understanding and implementing best clocking for the design using Cadence/Synopsys EDA tools Analyzing and ensuring design closure for STA using tools like SynopsysPrimeTime or Cadence Innovus/Tempus Leveraging physical Design Verification using tools like Calibre for Layout updates to ensure design meets DRC/ LVS requirements

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