Custom Library Design Lead
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- Have you previously worked at Apple?
About this role
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Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule?
Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality.
You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned.
Be a part of an exciting silicon design group that is responsible for crafting state-of-the-art ASICs. We have an extraordinary opportunity for Circuit Design Engineering Lead. In this highly visible role, you will be at the heart of a processor design effort, leading custom digital circuits team and library development, making a critical impact delivering products to market quickly.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers.
As a Library Design Engineering Lead for the custom circuits team, you will perform the following: Lead & mentor small team of highly talented circuit design engineers & provide technical guidance Drive design, development and characterization/QA of high performance, low power standard cells to improve chip design PPA. Drive development of power management cell designs that cater to Apple’s Low Power product requirements.
Identify next generation of new ideas to drive PPA improvements further engage with CPU, SOC and GPU teams on chip level integration requirements. Drive library checks & analysis, develop new methodologies based on new design requirements. Work with foundry on new technology requirements, drive layout dependent design optimization and layout checks.
Manage migration to new PDK, PDV of standard cells & releases Support and drive cellular library requirements. Engage with cellular teams to understand specific design needs and cater to those requirements.
BS and a minimum of 10 years of relevant industry experience.
We are looking for applicants with 10+ years of experience in Standard cells library development. Master's Degree preferred Proven experience in developing, driving & implementing design methodologies Proven experience leading and mentoring a small team Strong influence, excellent interpersonal skills & able to work with multi-functional teams Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso.
Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power Management Cells. Knowledge of agentic flows, familiarity with AI drive design optimization, checks, flows.