CPU Cache Microarchitect/RTL Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.

Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it.

Join us to help deliver groundbreaking Apple products!

Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:

• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Minimum BS and 10+ years of relevant industry experience

Experience with microprocessor architecture

Experience with logic design principles with timing and power implications

Experience in Verilog or VHDL

Experience with simulators and waveform debugging process

Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction

Understanding of low power microarchitecture techniques

Understanding of high-performance techniques and trade-offs in a CPU microarchitecture

Experience in C or C++ programming

Experience using an interpretive language such as Perl or Python